发明名称 |
Methods for forming interconnections between top electrodes in memory cells by a two-step chemical-mechanical polishing (CMP) process |
摘要 |
Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material. |
申请公布号 |
US9443763(B2) |
申请公布日期 |
2016.09.13 |
申请号 |
US201314025537 |
申请日期 |
2013.09.12 |
申请人 |
Micron Technology, Inc. |
发明人 |
Sciarrillo Samuele |
分类号 |
H01L21/768;H01L45/00;H01L27/24 |
主分类号 |
H01L21/768 |
代理机构 |
Brooks, Cameron & Huebsch, PLLC |
代理人 |
Brooks, Cameron & Huebsch, PLLC |
主权项 |
1. A method for forming an array of memory cells, comprising:
forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode; forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures; etching-back the interconnection conductive material; forming a dielectric material over the interconnection conductive material after etching-back and over a reference level adjacent the plurality of vertical structures; chemical mechanical polishing (CMPing) the dielectric material to remove a first portion of the dielectric material from over the interconnection conductive material while keeping a second portion of the dielectric material over the reference level; and forming a conductive line over the interconnection conductive material after etching-back the interconnection conductive material. |
地址 |
Boise ID US |