Power-On-Reset Detector

摘要

Various implementations described herein are directed to an integrated circuit for power-on-reset detection. The integrated circuit may include a first stage configured to receive an input voltage signal and provide a triggering signal during ramp of the input voltage signal. The integrated circuit may include a second stage configured to receive the triggering signal from the first stage and provide an output voltage signal during ramp of the input voltage signal via gate leakage through at least one transistor.

主权项

1. An integrated circuit, comprising:
a first stage having a resistor and a capacitor arranged to receive an input voltage signal and provide a triggering signal during ramp of the input voltage signal; and a second stage having at least one transistor arranged to receive the triggering signal from the first stage and provide an output voltage signal during ramp of the input voltage signal via gate leakage through the at least one transistor, wherein the at least one transistor is intercoupled to function as a capacitor having high gate input resistance.