Data processing apparatus and method for controlling use of an issue queue to represent an instruction suitable for execution by a wide operand execution unit

摘要

An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

主权项

1. A data processing apparatus, comprising:
execution circuitry comprising a number of execution units, including a first operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction, where N is an integer greater than 0; decoder circuitry configured to decode each instruction to be executed by the execution circuitry in order to generate for each instruction at least one control data block identifying an operation to be performed by the execution circuitry in order to execute said instruction; issue queue circuitry providing an issue queue having a plurality of slots, each slot configured to store one control data block generated by the decoder circuitry along with up to M bits of operand data associated with that control data block, where M is less than N and is an integer greater than 0; the issue queue circuitry configured to issue control data blocks and associated operand data from the issue queue to the execution circuitry for processing; the decoder circuitry being responsive to receiving an instruction suitable for execution by said first operand execution unit and requiring more than M bits, but no more than N bits, of operand data to be processed during execution, to generate at least two re-combineable control data blocks for said instruction suitable for execution by said first operand execution unit; the issue queue circuitry configured to allocate a slot in the issue queue for each of said at least two re-combineable control data blocks and up to M bits of associated operand data, and to mark those allocated slots to identify that they contain re-combineable control data blocks; the issue queue circuitry being configured, responsive to a determination that said at least two re-combineable control data blocks are to be issued to said first operand execution unit, to re-combine said at least two re-combineable control data blocks into a combined control data block, and to issue the combined control data block to said first operand execution unit along with the operand data contained in each of the allocated slots for said at least two re-combineable control data blocks.