发明名称 |
VERTICALLY INTEGRATED MEMORY CELL |
摘要 |
A method of forming a vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench, and a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor is in direct contact with and electrically coupled to the trench capacitor. |
申请公布号 |
US2016365291(A1) |
申请公布日期 |
2016.12.15 |
申请号 |
US201615246861 |
申请日期 |
2016.08.25 |
申请人 |
International Business Machines Corporation |
发明人 |
Barth, JR. John E.;Khan Babar A. |
分类号 |
H01L21/84;H01L29/66;H01L49/02;H01L27/12;H01L21/762 |
主分类号 |
H01L21/84 |
代理机构 |
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代理人 |
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主权项 |
1. A method of forming a vertically integrated memory cell comprising:
forming a deep trench extending into a semiconductor-on-insulator substrate comprising an SOI layer, a buried oxide layer, and a base layer; the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer electrically insulates the SOI layer from the base layer; forming a trench capacitor located within the deep trench; and forming a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor is in direct contact with and electrically coupled to the trench capacitor, and a gate of the vertical transistor is located within the SOI layer and surrounds the deep trench. |
地址 |
Armonk NY US |