发明名称 |
Method of forming a capacitor and a capacitor formed using the method |
摘要 |
An integrated circuit including a capacitor and a method of manufacturing the capacitor simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings corresponding to vias and capacitors extend through a second interlevel dielectric to the first interconnect layer. A conductor is deposited in the via openings. An insulator is deposited in the openings and on the conductor in the via openings. A trench is then etched into the upper portion of the via openings while simultaneously removing the insulator from the conductor in the via openings. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.
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申请公布号 |
US6025226(A) |
申请公布日期 |
2000.02.15 |
申请号 |
US19980007904 |
申请日期 |
1998.01.15 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GAMBINO, JEFFREY P.;JASO, MARK A.;KOTECKI, DAVID E. |
分类号 |
H01L21/02;H01L21/768;H01L21/8242;H01L27/08;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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