III-V device with overlapped extension regions using replacement gate

摘要

A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a replacement gate process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having multiple layers and a T-shaped gate structure using a gate replacement process. The T-shaped gate structure may be formed with a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the III-V compound semiconductor-containing heterostructure. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure.

主权项

1. A semiconductor structure, comprising:
a III-V compound semiconductor-containing heterostructure above a substrate, wherein the III-V compound semiconductor-containing heterostructure comprises a buffer layer above the substrate, a channel layer above and in contact with the buffer layer, a barrier layer above and in contact with the channel layer, and an etch stop layer above and in contact with the barrier layer; gate spacers on an uppermost surface of the etch stop layer; raised source-drain (RSD) regions on the uppermost surface of the etch stop layer, wherein the RSD regions are adjacent to and contacting the gate spacers; a dielectric layer on the uppermost surface of the RSD regions, wherein the dielectric layer is adjacent to and contacting the gate spacers, and wherein an uppermost surface of the dielectric layer is higher than an uppermost surface of the gate spacers; and a T-shaped gate structure above the uppermost surface of the channel layer and adjacent to the gate spacers, wherein the T-shaped gate structure comprises:
a narrow bottom portion extending from the uppermost surface of the gate spacers to no further than a lowermost portion of the barrier layer, the narrow bottom portion having sidewalls that are substantially flush with sidewalls of the gate spacers, anda wide upper portion that extends from the uppermost surface of the gate spacers to the uppermost surface of the dielectric layer, the wide upper portion having a lowermost surface only in contact with the uppermost surface of the gate spacers.