发明名称 Method of and apparatus for testing semiconductor memory
摘要 A failure analysis memory for storing failure information representative of a test result of a semiconductor memory under test is divided into a plurality of blocks with compacted addresses, and a compaction memory having areas corresponding respectively to the blocks of the failure analysis memory is prepared. Data indicative of a failure cell in any one of the blocks of the failure analysis memory is written in an area of the compaction memory which corresponds to the any one of the blocks. Minimum and maximum addresses of addresses at which failure cells are present in the blocks are determined, and failure data is read from the failure analysis memory in a range between the minimum and maximum addresses of each of the blocks, which correspond to the areas of the compaction memory which store the data indicative of a failure cell.
申请公布号 US5854796(A) 申请公布日期 1998.12.29
申请号 US19970861344 申请日期 1997.05.21
申请人 ADVANTEST CORPORATION 发明人 SATO, SHINYA
分类号 G01R31/28;G01R31/3193;G11C29/00;G11C29/40;G11C29/44;(IPC1-7):G06F11/00 主分类号 G01R31/28
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