| 摘要 |
<p>The silicon wafer (54) of a wafer-scale-integrated assembly is doped to render it highly conductive. Additionally, a conductive layer (56) is formed on the bottom of the wafer. The bottom-side layer forms an easily accessible ground plane of the assembly. Moreover, this layer and the conductive silicon constitute one plate of an advantageous wafer-size decoupling capacitor. A nearly continuous power layer (58) and a relatively thick layer (60) of silicon dioxide on the top side of the assembly form the other elements of the decoupling capacitor. Additionally, the nearly continuous power layer constitutes an effective a-c ground plane for overlying signal lines.</p> |
