| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce the scale of a quantization circuit which is used when an MPEG-4 encoder is formed and so on, to reduce the area of an LSI chip in which this circuit is formed, and to reduce its power consumption. <P>SOLUTION: A dc<SB>-</SB>scaler table 4, a reciprocal table 5 which stores a number of an order lower than (1)<SB>2</SB>being at an uppermost order bit of the effective fixed decimal point number of the reciprocal of a divisor, concerning the reciprocal of the divisor of a second quantization processing formula, and a quantity of a shift from the bit of 2<SP>0</SP>of this (1)<SB>2</SB>, a selection circuit 6, a multiplication circuit 7, and a shift circuit 8 are provided. The dividend of a second quantization processing formula is multiplied by a number obtained by adding (1)<SB>2</SB>to the upper order of a number which the reciprocal table 5 stores. Moreover, quantized DCT coefficients are computed by shifting the multiplication result by a necessary amount, on the basis of the quantity of the shift which the reciprocal table 5 stores. <P>COPYRIGHT: (C)2004,JPO</p> |
