DATA PROCESSING SYSTEM ARCHITECTURE

摘要

The control unit periodically monitors, in synchronism with internal CPU cycles if memory access requests from the input/ output processors synchronism with its internal cycles without preamble dialogue and access waiting time. If I/OP memory access requests are pending, the control unit grants access to one I/OP on a priority basis, activates a memory cycle and monitors in time relation with the memory cycle. If other I/OP memory access requests are pending, the control unit grants further memory access without delay at the end of the cycle.