发明名称 |
Small-sized light-emitting diode chiplets and method of fabrication thereof |
摘要 |
Diode includes light emitting region, first metal layer, dielectric layer, and second metal layer. Light emitting diode includes n-type group III-nitride portion, p-type group III-nitride layer, and light emitting region sandwiched between n- and p-type layers. First metal layer may be coupled to p-type III-N portion and plurality of first terminals. First metal layer and p-type III-N portion may have substantially similar lateral size that is smaller than 200 micrometers. A portion of light emitting region and first metal layer may include a single via. Electrically-insulating layer may be coupled to first metal layer and sides of the single via. First terminals may be exposed from electrically-insulating layer. Second metal layer may include second terminal and may be coupled to electrically-insulating layer and to n-type III-N portion through the single via. The thickness of the diode excluding second terminal may be between 2 and 20 micrometers. Other embodiments are described. |
申请公布号 |
US9640732(B2) |
申请公布日期 |
2017.05.02 |
申请号 |
US201615003251 |
申请日期 |
2016.01.21 |
申请人 |
Palo Alto Research Center Incorporated |
发明人 |
Wunderer Thomas;Chua Christopher L.;Johnson Noble M. |
分类号 |
H01L33/48;H01L33/32;H01L33/20;H01L33/38;H01L27/15;H01L33/00;H01L33/14 |
主分类号 |
H01L33/48 |
代理机构 |
Blakely Sokoloff Taylor & Zafmann LLP |
代理人 |
Blakely Sokoloff Taylor & Zafmann LLP |
主权项 |
1. A diode chiplet comprising:
an n-type group III-nitride portion, a p-type group III-nitride layer, and a group III-nitride light emitting region sandwiched between the n- and p-type portion; a first metal layer having a bottom side coupled to the p-type III-N layer and a top side including a first terminal, the bottom side of the first metal layer has a lateral size that is substantially equal to the p-type III-N layer, the first terminal being centrally located above the light emitting region; an electrically-insulating layer directly coupled to the top side of the first metal layer, sides of the first metal layer and sides of the p-type III-N layer, sides of the light emitting region, and sides of a first part of the n-type III-N layer, wherein the first terminal and sides of a second part of the n-type III-N layer are exposed from the electrically-insulating layer, wherein the sides of the first part of the n-type III-N layer are respectively (i) parallel to the sides of the second part of the n-type III-N layer and (ii) directly connected in line with the sides of the second part of the n-type III-N layer; and a second metal layer including a second terminal directly coupled to the electrically-insulating layer and to the sides of the second part of the n-type III-N portion, wherein the second metal layer is directly coupled to a top side of a portion of the electrically-insulating layer that is coupled to the top side of the first metal layer, wherein a perimeter of the diode chiplet is smaller than 600 micrometers and a thickness of the diode chiplet excluding the second terminal is between 2 and 20 micrometers. |
地址 |
Palo Alto CA US |