发明名称 DIGITAL SIGNAL PROCESSOR
摘要 PURPOSE:To access most efficiently a data sequence in a data memory by giving an address by plural registers out of general registers and using remainder registers for arithmetic of signal processing. CONSTITUTION:Data to be calculated, constants required for arithmetic, etc. are stored in data memopries X4 and Y10. The address of the data memory X4 is supplied by selecting one of 6 general registers 18. Thereafter, a constant 8 or contents of an increment register 9 are added to this address value, and the result is stored in the same register. Though the whole of registers is shared between modification of the address to the data memory X4 and arithmetic in an ALU 15, this modification is performed independently of this arithmetic in the ALU 15. A flag 19 detects zero or outputs a sign bit in accordance with the output value of an adder 7, and judgement by the adder 7 is made possible. The address of the data memory Y10 is given by an address counter 11, and contents of the address counter 11 are incremented automatically by the control.
申请公布号 JPS61282933(A) 申请公布日期 1986.12.13
申请号 JP19850124516 申请日期 1985.06.07
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KANO YASUO
分类号 G06F9/34;G06F7/00;G06F9/38;G06F17/10 主分类号 G06F9/34
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