| 摘要 |
<p>A MOS device having a vertical gate electrode (34) and a planar top surface. The gate electrode material (33) fills a rectangular groove (31) lined with a dielectric material (32) which extends downward so that source (21a, 21b) and body (20a, 20b) regions lie on each side of the groove (31). An insulating layer (35) is formed over the gate structure so that a device with a planar top surface is obtained. In operation, carriers flow vertically between the source (21a, 21b) and drain (10, 11) regions through channel regions (22c1, 22c2). </p> |
