| 摘要 |
A direct memory access controller (DMAC) comprises a chain DMA mode (which does not require a predetermined software process) and a normal DMA mode (which requires a predetermined software process). When a communication apparatus is in a normal-reception state, data is received utilizing the chain DMA mode and when the apparatus is in a reception-busy state, data is received utilizing the normal DMA mode. By virtue of this feature, in a normal data reception, a memory designated as a DMA transfer destination is switched without delay which will be caused by a software process, thereby preventing overflows of received data due to overhead required by a CPU.
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