| 摘要 |
PURPOSE:To obtain a C-IGFET logic circuit featuring a small amount of the power consumption by inserting P- and N-channel IGFET's between the drains of P- and N-channel IGFET circuits which are used in pairs and thus reducing the logic amplitude. CONSTITUTION:When input IN is at a low potential, P-channel IGFETP11 is turned on to charge load capacity C1. And voltage VOH of output OUT rises up only to the level decided by power voltage VDD - VTHP owing to the voltage drop of threshold voltage VTHP of P-channel IGFETP12. When input IN is at a high potential, N-channel IGFETN11 is turned on to discharge the charge stored in capacity C1. And voltage VOL occurring at the output is lowered down only to the level decided by VTHN owing to voltage drop of VTHN of N-channel IGFETN12. In other words, amplitude V of OUT reduces as V = VDD - VTHP - VTHN. As the current flowing to GND from the power source is proportional to V, the power consumption can be reduced. |
