发明名称 |
Power semiconductor device |
摘要 |
An object is to provide a technique in which a cost reduction in a power semiconductor device can be achieved while maintaining heat dissipation performance as much as possible. A power semiconductor device includes a leadframe, a power semiconductor element disposed on an upper surface of the leadframe, and an insulating layer disposed on a lower surface of the leadframe. At least a partial line of a peripheral line of a region where the insulating layer is disposed, on the lower surface, is aligned, in top view, with at least a partial line of an expanded peripheral line obtained by shifting outwardly, by the amount corresponding to the thickness of the leadframe, the peripheral line of the region where the power semiconductor element is disposed, on the upper surface. |
申请公布号 |
US9627302(B2) |
申请公布日期 |
2017.04.18 |
申请号 |
US201415021413 |
申请日期 |
2014.01.10 |
申请人 |
Mitsubishi Electric Corporation |
发明人 |
Ichikawa Keitaro;Shikano Taketoshi |
分类号 |
H01L23/495;H05K7/18;H01L21/00;H01L25/07;H01L25/18;H01L23/31 |
主分类号 |
H01L23/495 |
代理机构 |
Studebaker & Brackett PC |
代理人 |
Studebaker & Brackett PC |
主权项 |
1. A power semiconductor device comprising:
a leadframe; a power semiconductor element disposed on a first main surface of said leadframe; and an insulating member disposed on a second main surface, opposite to said first main surface, of said leadframe, wherein at least an edge of said insulating member is aligned, in top view, with at least a partial line of an expanded peripheral line, said expanded peripheral line being obtained by shifting outwardly, by an amount corresponding to a thickness of said leadframe, a peripheral line of a region where said semiconductor element is disposed, on said first main surface. |
地址 |
Tokyo JP |