发明名称 |
Multiprocessor system with improved secondary interconnection network |
摘要 |
Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network. |
申请公布号 |
US9612984(B2) |
申请公布日期 |
2017.04.04 |
申请号 |
US201615043905 |
申请日期 |
2016.02.15 |
申请人 |
COHERENT LOGIX, INCORPORATED |
发明人 |
Dobbs Carl S.;Trocino Michael R. |
分类号 |
G06F13/36;H04L12/56;G06F13/362;G06F13/40;G06F15/173;G06F15/78 |
主分类号 |
G06F13/36 |
代理机构 |
Meyertons Hood Kivlin Kowert & Goetzel, P.C. |
代理人 |
Meyertons Hood Kivlin Kowert & Goetzel, P.C. ;Hood Jeffrey C. |
主权项 |
1. A multiprocessor system, comprising:
a plurality of processors, each comprising a plurality of processor ports; a plurality of memories; a plurality of routers, wherein the plurality of routers form a primary interconnection network; wherein the plurality of processors, the plurality of memories and the plurality of routers are coupled together in an interspersed fashion; a plurality of interface units, wherein each interface unit is coupled to a respective processor and a respective router; wherein the plurality of interface units are coupled together to form a secondary interconnection network; and a bus controller coupled to at least one specified interface unit, wherein the bus controller is configured to: send data to and receive data from the at least one specified interface unit; arbitrate requests for access to the at least one specified interface unit; and perform a comparison between messages received from each of two or more processors and perform a particular one of a plurality of actions based upon results of the comparison. |
地址 |
Austin TX US |