发明名称 PROGRAMMABLE ON-DIE TERMINATION TIMING IN A MULTI-RANK SYSTEM
摘要 On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.
申请公布号 US2017093400(A1) 申请公布日期 2017.03.30
申请号 US201514865866 申请日期 2015.09.25
申请人 Intel Corporation 发明人 Bains Kuljit S.;Kostinsky Alexey;Bonen Nadav
分类号 H03K19/0175;G06F3/06;G06F13/16 主分类号 H03K19/0175
代理机构 代理人
主权项 1. A memory device with on-die termination (ODT) comprising: a hardware interface to couple to a memory bus shared by multiple memory devices organized as ranks of memory; and logic to receive a memory access command on the memory bus, the memory access command directed to a target rank to execute the command, the logic to further selectively engage ODT for the memory access operation in accordance with an ODT latency setting in response to receipt of the memory access command; wherein the ODT latency setting includes a programmable setting to set different ODT timing values for Read and Write transactions.
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