Method for co-designing flip-chip and interposer

摘要

A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip.

主权项

1. A method for co-designing a flip-chip and an interposer, comprising:
obtaining information regarding I/O pads, power pins and IR constraints of the flip-chip by a processor; performing a bump planning procedure by the processor to obtain a minimum number of power bumps of the flip-chip corresponding to the power pins of the flip-chip according to the information, and to uniform power density of the power bumps of the flip-chip to obtain a minimum conductance of each of the power pins of the flip-chip and a bump placement of a plurality of micro bumps of the flip-chip; performing a chip-interposer routing procedure by the processor to obtain a flow network according to the minimum conductance of the power pins and the bump placement of the micro bumps, and obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the flow network; and mounting the flip-chip to the interposer according to the RDL routing of the flip-chip and the interposer routing of the interposer to obtain a chip-interposer structure, wherein a distance between a die boundary of the flip-chip and the micro bump adjacent to the die boundary of the flip-chip is not greater than half of a bump pitch of the micro bumps in the bump placement.