Synchronization of outputs from multiple digital-to-analog converters

摘要

Disclosed systems include a clock-multiplying phase locked loop (PLL) generating a clock signal for a DAC comprising a plurality of DAC cells, the systems configured to control that a phase of the DAC output has a predefined relation to a phase of a PLL input reference clock. An exemplary system incorporates an auxiliary DAC cell implemented as a replica of one of the DAC cells of the DAC and operation of the DAC and the auxiliary DAC cell is timed with the same clock signal generated by the PLL, so that outputs of the auxiliary cell and the DAC are phase synchronized by design. The system is configured to ensure that a phase of the auxiliary DAC cell output is related to the phase of the PLL reference clock, which results in a phase of the DAC output also being related to the phase of the PLL reference clock.

主权项

1. A system comprising:
a digital-to-analog converter (DAC) comprising a plurality of DAC cells; an auxiliary DAC cell comprising a replica of one of the plurality of DAC cells; a clock-multiplying phase locked loop (PLL) configured to receive a PLL reference clock signal and generate an output clock signal having a frequency greater than that of the PLL reference clock signal, wherein the output clock signal is configured to time operation of each of the plurality of DAC cells and of the auxiliary DAC cell; and phase alignment means for controlling a phase of an output generated by each of the DAC and the auxiliary DAC cell to be at a predefined phase difference from a phase of the PLL reference clock signal.