| 摘要 |
A processor 605, such as a heterogeneous multi-core processor, includes a binary translation (BT) engine 645 having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache 648. The binary translator may be isolated from a software stack and transparent thereto by way of means such as concealed memory 640. The binary translated code may include a routine to emulate an instruction not provided in the target ISA such as an instruction with a vector operand wherein a width of a datapath of the target core is less than a width of the vector operand. The processor may include a first and second core for executing instructions of a first ISA and a second ISA respectively wherein the second ISA may be different to the first ISA or a subset thereof. The second core may have lower power consumption than the first core and the binary translation may be from the first ISA to the second ISA. |
