Selective suppression of instruction cache-related directory access

摘要

Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is in a same cache line of the instruction cache as a last instruction fetch; and based, at least in part, on determining that the next instruction fetch is in the same cache line, suppressing for the next instruction fetch one or more instruction cache-related directory accesses, and forcing for the next instruction an address match signal for the same cache line. The suppressing may include generating a known-to-hit signal where the next fetch is in the same cache line, and the last fetch is not a branch instruction, and issuing an instruction cache hit where a cache line segment of the same cache line having the next instruction has a valid validity bit, the valid validity bit having been retrieved and maintained based on a most-recent, instruction cache-directory-accessed fetch.

主权项

1. A method of processing an instruction fetch from an instruction cache, the method comprising:
determining for a next instruction fetch whether the next instruction fetch is in a same cache line of the instruction cache as a last instruction fetch from the instruction cache; based, at least in part, on determining that the next instruction fetch is in the same cache line, suppressing for the next instruction fetch one or more instruction cache-related directory accesses, and forcing for the next instruction fetch an address match signal for the same cache line; and wherein suppressing the one or more instruction cache-directory accesses comprises suppressing for the next instruction fetch an instruction directory (IDIR) lookup associated with the instruction cache, and suppressing for the next instruction fetch an instruction address translation directory lookup associated with the instruction cache.