发明名称 Scalable room temperature quantum information processor
摘要 A quantum information processor (QIP) may include a plurality of quantum registers, each quantum register containing at least one nuclear spin and at least one localized electronic spin. At least some of the quantum registers may be coherently coupled to each other by a dark spin chain that includes a series of optically unaddressable spins. Each quantum register may be optically addressable, so that quantum information can be initialized and read out optically from each register, and moved from one register to another through the dark spin chain, though an adiabatic sequential swap or through free-fermion state transfer. A scalable architecture for the QIP may include an array of super-plaquettes, each super-plaquette including a lattice of individually optically addressable plaquettes coupled to each other through dark spin chains, and separately controllable by confined microwave fields so as to permit parallel operations.
申请公布号 US9317473(B2) 申请公布日期 2016.04.19
申请号 US201113991159 申请日期 2011.12.14
申请人 PRESIDENT AND FELLOWS OF HARVARD COLLEGE 发明人 Yao Norman Y.;Jiang Liang;Gorshkov Alexey V;Maurer Peter C;Giedke Geza;Cirac Juan Ignacio;Lukin Mikhail D.
分类号 G11C11/00;G06F15/78;B82Y10/00;G06N99/00 主分类号 G11C11/00
代理机构 Elizabeth Kim Patent Law Offices LLC 代理人 Elizabeth Kim Patent Law Offices LLC
主权项 1. A quantum information processor, comprising: a plurality of quantum registers, each quantum register containing at least one nuclear spin and at least one electronic spin; wherein at least some of the quantum registers are coherently coupled to each other by a dark spin chain; wherein quantum information can be optically read out from each quantum register and optically initialized at each quantum register, and moved from one quantum register to another through the dark spin chain; wherein the quantum registers are spatially separated from each other by a distance sufficient to permit individual optical initialization and readout; and wherein the quantum information processor has a scalable architecture that permits simultaneous single- and two-qubit gate operations to be performed in parallel at room temperature, the scalable architecture comprising: an array of super-plaquettes, each super-plaquette including a two dimensional lattice of individually optically addressable plaquettes coupled to each other through dark spin chains, each plaquette containing a single quantum register; wherein each super-plaquette is separately controllable by confined microwave fields so as to permit parallel operations; and wherein the quantum information is movable between the boundaries of different super-plaquettes within the array by localized microwave fields of a dual super-plaquette lattice.
地址 Cambridge MA US