I/O pin capacitance reduction using TSVs

摘要

Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and unselected die of a plurality of stacked die are described. A reduction in pin capacitance allows for faster switching times and/or lower power operation. In some embodiments, a TSV may connect an internal node (e.g., the output of a pre-driver) within a selected die of a plurality of stacked die with the input of an off-chip driver within an unselected die of the plurality of stacked die. In some cases, only a single die within a die stack may be selected (or enabled) at a given time. Using a TSV to connect internal nodes associated with off-chip drivers located within both selected and unselected die of the die stack allows for reduced off-chip driver sizing and thus reduced pin capacitance.

主权项

1. A non-volatile storage system, comprising:
a first memory die; and a second memory die located above the first memory die, the first memory die includes a first off-chip driver and the second memory die includes a second off-chip driver, the first memory die includes a first pre-driver that is in a first input signal path of the first off-chip driver, the first pre-driver connects to a second input signal path of the second off-chip driver via a vertical electrical connection between the first memory die and the second memory die, the vertical electrical connection includes a TSV that extends vertically through a substrate of the second memory die.