| 摘要 |
The invention provides a semiconductor package assembly including a system-on-chip (SOC) package. The SOC package includes a logic die having first pads thereon. A first redistribution layer (RDL) structure is coupled to the logic die. A molding compound surrounds the logic die, being in contact with the first RDL structure and the logic die. A dynamic random access memory (DRAM) package is stacked on the SOC package. The DRAM package includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface. A dynamic random access memory (DRAM) die is mounted on the die-attach surface, coupled to the body through the bonding wires. One of the SOC package and the DRAM package includes an additional dynamic random access memory (DRAM) die embedded therein. The additional DRAM die has through silicon via (TSV) interconnects formed through the additional DRAM die. |
