| 发明名称 |
Method of Manufacturing a Vertical Junction Field Effect Transistor |
| 摘要 |
A method of manufacturing a vertical junction field effect transistor (JFET) includes forming a drain in a semiconductor substrate, forming a compound semiconductor epitaxial layer on the semiconductor substrate, and forming a source, a gate, a drift region, and a body diode all in the same compound semiconductor epitaxial layer. The drain is vertically spaced apart from the source and the gate by the drift region. The body diode is connected between the drain and the source. |
| 申请公布号 |
US2016064534(A1) |
申请公布日期 |
2016.03.03 |
| 申请号 |
US201514935139 |
申请日期 |
2015.11.06 |
| 申请人 |
Infineon Technologes Austria AG |
发明人 |
Esteve Romain;Ouvrard Cédric |
| 分类号 |
H01L29/66;H01L21/04;H01L21/02 |
主分类号 |
H01L29/66 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of manufacturing a vertical junction field effect transistor (JFET), the method comprising:
forming a drain in a semiconductor substrate; forming a compound semiconductor epitaxial layer on the semiconductor substrate; and forming a source, a gate, a drift region, and a body diode all in the same compound semiconductor epitaxial layer, the drain being vertically spaced apart from the source and the gate by the drift region, the body diode being connected between the drain and the source. |
| 地址 |
Villach AT |
