Through-package-via (TPV) structures on inorganic interposer and methods for fabricating same

摘要

Aspects of the present disclosure generally relate to a microelectronic package including a plurality of through vias having walls in a glass interposer having a top portion and a bottom portion. The microelectric package may also include a stress relief barrier on at least a portion of the top and bottom portions of the glass interposer. The microelectric package may further include a metallization seed layer on at least a portion of the stress relief layer and a conductor on at least a portion of the metallization seed layer. The conductor extends through at least a portion of the plurality of the through vias, forming a plurality of metalized through package vias. At least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.

主权项

1. A microelectronic package comprising:
a plurality of through vias having walls in a glass interposer having a top portion and a bottom portion; a stress relief barrier on at least a portion of the top and bottom portions of the glass interposer, wherein the stress relief barrier on at least the bottom portion of the glass interposer forms a single, continuous layer from about a first through via of the plurality of through vias to about a second through via of the plurality of through vias; a metallization seed layer on at least a portion of the stress relief layer; and a conductor on at least a portion of the metallization seed layer and through at least a portion of the plurality of the through vias forming a plurality of metalized through package vias, wherein at least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.