A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
申请公布号
WO2016016726(A2)
申请公布日期
2016.02.04
申请号
WO2015IB01805
申请日期
2015.07.27
申请人
LINEAR ALGEBRA TECHNOLOGIES LIMITED
发明人
BARRY, BRENDAN;CONNOR, FERGAL;O'RIORDAN, MARTIN;MOLONEY, DAVID;POWER, SEAN