INTEGRATION METHOD FOR DUAL DOPED POLYSILICON GATE PROFILE AND CD CONTROL

摘要

In accordance with the present teachings, methods of making dual doped polysilicon gates are provided. The method can include providing a semiconductor structure including a plurality of polysilicon gates having a first critical dimension disposed over a dielectric layer and planarizing the plurality of polysilicon gates with a spin-on material to form a plurality of planarized polysilicon gates. The method can further include doping an exposed first region with p-type dopants to form a plurality of p-doped planarized polysilicon gates and doping an exposed second region with n-type dopants to form a plurality of n-doped planarized polysilicon gates. The method can also include removing the spin-on material to form a plurality of p-doped polysilicon gates and a plurality of n-doped polysilicon gates, wherein critical dimension of each of the plurality of n-doped polysilicon gates and the plurality of p-doped polysilicon gates are substantially similar to the first critical dimension.