发明名称 演算装置
摘要 <p>According to an embodiment, an arithmetic device includes an arithmetic processing unit, an address generating unit, and a control unit. The arithmetic processing unit performs a plurality of arithmetic processing used in an encryption method. Based on an upper bit of the address of the first piece of data and based on an offset which is a value corresponding to a counter value and which is based on the address of the first piece of data, the address generating unit generates addresses of the memory device. The control unit controls the arithmetic processing unit in such a way that the arithmetic processing is done in a sequence determined in the encryption method, and that specifies an update of the counter value at a timing of modifying the type of data and at a timing of modifying data.</p>
申请公布号 JP5755970(B2) 申请公布日期 2015.07.29
申请号 JP20110184938 申请日期 2011.08.26
申请人 发明人
分类号 G09C1/00 主分类号 G09C1/00
代理机构 代理人
主权项
地址