发明名称 Modeless instruction execution with 64/32-bit addressing
摘要 A method comprises receiving a value expressed by a number of bits expressed by a number of bits equal to a general-purpose register width (e.g. 64 bits); determining whether the value is within a pre-determined range, and using only a least significant portion of the value having a pre-determined number of bits (e.g. 32 bits) to perform an arithmetic operation; and sign-extending a result of the arithmetic operation to use as an effective address for instruction execution. An immediate value may be decoded from the instruction, and the operation may be adding the immediate to the least significant portion of the value. The pre-determined ranges may be defined by most-significant bits (MSB) being all binary 1 (one) or all binary 0 (zero); where the MSBs are bits from a general-purpose register not included within the least significant portion. An address calculation unit may be provided in an instruction fetch unit, with the effective address used as a location from which to fetch instructions. If the value is not within a pre-determined range, the value may be treated as a double-word sized value, with arithmetic operation performed using double-word sized value and not sign-extending a result of the operation.
申请公布号 GB2525473(A) 申请公布日期 2015.10.28
申请号 GB20150003097 申请日期 2015.02.24
申请人 IMAGINATION TECHNOLOGIES LIMITED 发明人 RANJIT ROZARIO;RANGANATHAN SUDHAKAR
分类号 G06F9/355;G06F9/30;G06F9/34 主分类号 G06F9/355
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