Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

摘要

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

主权项

1. A system, comprising:
a first processor chip configured to include a first single-ended signaling interface circuit; a graphics processing cluster (GPC) chip that includes a multi-threaded processor core configured to execute graphics shader programs and a second single-ended interface circuit; a multi-chip module (MCM) package configured to include the first processor chip, the GPC chip, and an interconnect circuit, wherein the interconnect circuit comprises a first interconnect chip and a second interconnect chip that is coupled to the first interconnect chip and configured to transmit an access request from a second processor chip to the first interconnect chip; a first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit; a second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit; a memory controller chip that is configured to perform read-modify-write operations to a frame buffer memory and includes a third single-ended signaling interface circuit, wherein the first interconnect chip is configured to transmit the access request to the memory controller chip and the memory controller chip is configured to reply to the access request; and a third set of electrical traces fabricated within the MCM package and configured to couple the third single-ended signaling interface circuit to the interconnect circuit.