MEMORY SYSTEM, AND SEMICONDUCTOR MEMORY DEVICE AND CONTROLLER THEREOF

摘要

A memory system, and a semiconductor memory device and a controller thereof is provided to improve error of data input/output by inputting/outputting data in response to internal write clock signal. A synchronous circuit(32) controls a phase of a write clock signal(WCK), and the clock signal generator generates the clock signal. A divider(42) generates output clock signal(w1-wm) by dividing the write clock signal, and a phase detector(44) generates an up/down signal(UP/DN) by detecting the phase difference between a clock signal and one of the internal clock signal(W). The phase controller(46) generates the control signal(CON) which shows steady-state of the phase of the output clock signals or the inversed state if a rising edge of the output clock signal(Wn) is not generated. A phase correction unit(48) generates the internal write clock as the output clock signal according to the steady- state of the phase or the reversed-state.