| 摘要 |
A page buffer circuit of a flash memory device includes a plurality of page buffers connected to a predetermined number of bit lines, respectively, and also connected to a Y-gate circuit, the page buffers perform a read operation or a program operation at the same time in response to bit line control signals, bit line select signals and control signals. Each of page buffers included in a page buffer circuit selectively gains access to one of memory cells connected to a predetermined number of bit lines, respectively. As a result, coupling capacitance component between sensing nodes can be reduced and the overall chip size can be reduced.
|
