| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a serial receiving circuit which can suppress the generation of bit errors resulting from long cycle jitters by suppressing power consumption. <P>SOLUTION: The serial receiving circuit (2), which receives a serial signal in synchronization with a clock signal (CK3), samples the serial signals in synchronization with sampling phases with a plurality of phases (CLK(1)-CLK(N)) in which each phase has been shifted with respect to the clock signal, and based on the sampled signal, discriminates a sampling phase scarcely affecting a sampling result resulting from a phase variation of the serial signal as the optimum phase to perform a reception operation with a signal sampled by the optimum phase as received data. Further, the circuit has, as the discrimination operation of the optimum phase, a first mode (initial phase detection), and a second mode (phase tracking) which discriminates the optimality of the optimum phase discriminated in the first mode based on a sampling result obtained by reducing the number of samplings. <P>COPYRIGHT: (C)2011,JPO&INPIT |
