Mask level reduction for MOFET

摘要

A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.

主权项

1. A method of fabricating a thin film transistor and in-plane-switch LCD electrodes with reduced masking operations, the method comprising the steps of:
providing a substrate with a surface; patterning gate metal on the surface of the substrate to define a thin film transistor gate; forming a layer of gate dielectric over the gate and surrounding substrate surface; depositing a layer of semiconducting metal oxide on the layer of gate dielectric; patterning a channel protection layer on the semiconducting metal oxide overlying the gate, the channel protection layer being patterned to define a channel area in the semiconducting metal oxide above the gate and to expose the remaining semiconducting metal oxide; depositing at least a source/drain metal layer on the channel protection layer and a portion of the exposed semiconducting metal oxide defining an in-plane-switch area; etching through the source/drain metal layer to the channel protection layer above the gate to separate the source/drain metal layer into thin film transistor source and drain terminals, and etching through the semiconducting metal oxide layer in areas not covered by the source/drain metal layer; patterning an organic dielectric material on the thin film transistor source and drain terminals and at surrounding area of the first electrode for the in-plane-switch; using the patterned organic dielectric material, etching through the source/drain metal layer in the in-plane-switch area to expose the semiconducting metal oxide and define a first electrode for an in-plane-switch; depositing a passivation layer on the patterned organic dielectric material and the first electrode for the in-plane-switch; and patterning a layer of transparent electrically conductive material on the passivation layer defining a second electrode for the in-plane-switch overlying the first electrode.