发明名称 Power efficient Viterbi decoder
摘要 <p>The present invention can reduce power consumption at the time of tracing. The present invention provides a viterbi decoding apparatus for decoding convolution codes, which includes a path memory unit that stores one of two paths toward respective transition states of a convolution code, as a selected path, for a plurality of continuous time points, a tracing unit that traces a selected path stored in the path memory unit in a reversed-time direction, thereby decoding a convolution code at respective time points, each of the time points being prior to a predetermined trace-skipping period, and a control unit that controls the path memory unit, wherein the path memory unit has a storage area designed to store selected paths assuming respective transition states at respective time points, the storage area is divided into sub-areas from the lowest order of transition state, each of the sub-areas corresponding to predetermined number of bits, and reading data can be stopped for each sub-area, and the control unit designates sub-areas from which no selected path needs to be read at respective time points so as to stop reading data from the designated sub-areas.</p>
申请公布号 EP1739843(B1) 申请公布日期 2015.07.29
申请号 EP20060253258 申请日期 2006.06.23
申请人 SONY CORPORATION 发明人 MIYAUCHI, TOSHIYUKI;MIZUTANI, YUICHI
分类号 H03M13/41 主分类号 H03M13/41
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