Multi-petascale highly efficient parallel supercomputer

摘要

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

主权项

1. A massively parallel computing structure comprising:
a plurality of processing nodes interconnected by multiple independent networks, each processing node including a plurality of processing elements for performing computation or communication activity as required when performing parallel algorithm operations, a first of said multiple independent networks includes an n-dimensional torus network, n is an integer greater than 3, including communication links interconnecting said processing nodes for providing high-speed, low latency point-to-point and multicast packet communications among said processing nodes or independent partitioned subsets thereof; and, said n-dimensional torus network for enabling point-to-point, all-to-all, collective (broadcast, reduce) and global barrier and notification functions among said processing nodes or independent partitioned subsets thereof, wherein combinations of said multiple independent networks interconnecting said processing nodes are collaboratively or independently utilized according to bandwidth and latency requirements of an algorithm for optimizing algorithm processing performance, wherein each said processing element is multi-way hardware threaded supporting transactional memory execution and thread level speculation, wherein said plurality of processing elements are configured to run speculative threads in parallel, wherein each processing element is further configured to:
communicate with a communications pathway, the pathway comprising a first level cache and a second level cache;switch between at least two modes of using the first and second level caches, both modes allowing the first level cache and/or a prefetch unit to be operated in a speculation blind manner, wherein the at least two modes comprise:a first mode where, responsive to a write from a speculative thread, at least one line corresponding to results is evicted from the first level cache and/or said prefetch unit and recorded in the second level cache; anda second mode where, responsive to a write from a speculative thread, the first level cache stores results, and wherein responsive to selection of the first mode, said processing element is configured to:
determine whether a speculative thread seeks to write;upon a positive determination, write from the speculative thread through the first level cache to the second level cache;evict a line from the first level cache and/or a prefetch unit corresponding to the writing; andresolve speculation downstream from the first level cache,wherein, subsequent to evicting a line, said processing element is further configured to:determine if a speculative thread seeks to access an address corresponding to the line in the first level cache, and if so,retrieve an appropriate version of data from the second level cache.