发明名称 Fault detection system, acquisition apparatus, fault detection method, program, and non-transitory computer-readable medium
摘要 It is a purpose of the invention to provide a fault detection system, etc., having improved fault coverage with a reduced number of test patterns to be input to a logic circuit. The fault detection system detects a fault in a logic circuit based on multiple output logic values of the logic circuit after a test input pattern is input. The output logic values are input to the logic circuit as an updated test input pattern. The system comprises: a first acquisition unit which acquires a part of or all of the output logic values; a comparison unit which compares the logic values acquired by the first acquisition unit with those predicted for when there are no faults, or for when there is a specific fault; and a fault judgment unit which judges whether or not there is a fault based on the comparison result obtained by the comparison unit.
申请公布号 US9075110(B2) 申请公布日期 2015.07.07
申请号 US201113877601 申请日期 2011.09.28
申请人 KYUSHU INSTITUTE OF TECHNOLOGY 发明人 Sato Yasuo;Kajihara Seiji
分类号 G01R31/3185;G01R31/3177 主分类号 G01R31/3185
代理机构 Rankin, Hill & Clark LLP 代理人 Rankin, Hill & Clark LLP
主权项 1. A fault detection system configured to detect a fault in a logic circuit based on a plurality of output logic values output from the logic circuit after a test input pattern is input, wherein the plurality of output logic values are input to the logic circuit as an updated test input pattern, the fault detection system comprising: a first acquisition unit configured to acquire a part of or otherwise all of the plurality of output logic values; a comparison unit configured to compare an output logic value acquired by the first acquisition unit with an output logic value expected when no fault is present in the logic circuit or otherwise an output logic value expected when a fault is present in the logic circuit; and a fault judgment unit configured to judge whether or not there is a specific fault in the logic circuit, based on a comparison result obtained by the comparison unit, wherein the plurality of output logic values are held by a holding unit comprising a plurality of individual holding units each configured to hold a single logic value, and wherein the first acquisition unit is configured to acquire a part of or otherwise all of the plurality of output logic values held by the holding unit, and wherein a part of or otherwise all of the output logic values respectively held by the plurality of individual holding units are acquired directly such that each output logic value is acquired from the corresponding individual holding unit without passing through the other individual holding units, the fault detection system further comprising a second acquisition unit configured to acquire a part of or otherwise all of the plurality of output logic values respectively held by the plurality of individual holding units via a different individual holding unit, wherein the comparison unit is configured to compare the output logic value acquired by the second acquisition unit with an output logic value expected when no fault is present in the logic circuit or otherwise an output logic value expected when a specific fault is present in the logic circuit, and wherein a number of times the first acquisition unit acquires the output logic value is greater than a number of times the second acquisition unit acquires the output logic value.
地址 Fukuoka JP