发明名称 FAST OPEN CIRCUIT DETECTION FOR OPEN POWER AND GROUND PINS
摘要 <p>A system and method for identifying opens among parallel connections on a circuit assembly such as a printed circuit board (PCB). In a learn phase performed on a known good circuit assembly, a group of parallel connected pins are excited with a first signal. A second signal, out-of-phase with the first signal, is applied to a second group of pins associated with the component. The amplitude and/or the phase of the second signal and the number and/or specific pins in the second group of pins are selected so that first and second signals coupled to a detector plate proximal to the component substantially offset. During a manufacturing test, signals of comparable amplitude and phase are applied to like pins on a like component of a circuit assembly under test. If the response signal coupled to a like detector plate is below a threshold, it is determined that each pin in the group of parallel connected pins is connected. If the amplitude of the response is over the threshold, one or more of the parallel pins is determined to be open. Additional tests may be performed to identify which of the parallel pins is likely open.</p>
申请公布号 EP2344899(B1) 申请公布日期 2015.06.10
申请号 EP20090826437 申请日期 2009.11.13
申请人 TERADYNE, INC. 发明人 SUTO, ANTHONY, J.
分类号 G01R31/28;G01R31/02;G01R31/04;G01R31/312;G01R31/3183;G01S13/00;H04M1/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址