发明名称 |
Method and structure of monolithically integrated IC and resistive memory using IC foundry-compatible processes |
摘要 |
The present invention relates to integrating a resistive memory device on top of an IC substrate monolithically using IC-foundry compatible processes. A method for forming an integrated circuit includes receiving a semiconductor substrate having a CMOS IC device formed on a surface region, forming a dielectric layer overlying the CMOS IC device, forming first electrodes over the dielectric layer in a first direction, forming second electrodes over the first electrodes in along a second direction different from the first direction, and forming a two-terminal resistive memory cell at each intersection of the first electrodes and the second electrodes using foundry-compatible processes, including: forming a resistive switching material having a controllable resistance, disposing an interface material including p-doped polycrystalline silicon germanium—containing material between the resistive switching material and the first electrodes, and disposing an active metal material between the resistive switching material and the second electrodes. |
申请公布号 |
US9036400(B2) |
申请公布日期 |
2015.05.19 |
申请号 |
US201314072657 |
申请日期 |
2013.11.05 |
申请人 |
Crossbar, Inc. |
发明人 |
Lu Wei |
分类号 |
G11C11/00;H01L27/24;G11C13/00;H01L45/00 |
主分类号 |
G11C11/00 |
代理机构 |
Ogawa P.C. |
代理人 |
Ogawa P.C. |
主权项 |
1. A monolithic integrated circuit and crossbar array comprising:
a semiconductor substrate having a first surface region; one or more CMOS integrated circuit devices provided on the surface region of the semiconductor substrate; a dielectric layer overlying the one or more CMOS integrated circuit devices; a first plurality of electrodes overlying the dielectric layer and extending along a first direction; a second plurality of electrodes overlying the first plurality of electrodes and extending along a second direction, wherein the first direction and the second direction are different; and wherein intersections of the first plurality of electrodes and the second plurality of electrodes define a two-terminal resistive memory cell comprising:
a resistive switching material having a controllable resistance; an interface material disposed between the resistive switching material and the first plurality of electrodes, wherein the interface material comprises a foundry-compatible p-doped polycrystalline silicon germanium—containing material; and an active metal material disposed between the resistive switching material and the second plurality of electrodes. |
地址 |
Santa Clara CA US |