发明名称 Method to adaptively calculate resistor mesh in IC designs
摘要 Using an adaptive square mesh for parasitic extraction, small squares of a predetermined minimum size will be placed where accuracy in the parasitic calculations is most critical—around edges, contacts and vias, and corners. Then, in areas where the parasitic analysis is less critical, for example in open spaces, a more coarse grid consisting of larger squares may be used to calculate the parasitic values in those spaces. Squares in the mesh may increase in size gradually to provide more accurate results.
申请公布号 US8984468(B1) 申请公布日期 2015.03.17
申请号 US201414230981 申请日期 2014.03.31
申请人 Cadence Design Systems, Inc. 发明人 Su Shun-Lin;Shu Yue-Zhong;Lo Chi-Yuan
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Kenyon & Kenyon LLP 代理人 Kenyon & Kenyon LLP
主权项 1. A method of simulating a resistor, comprising: creating, with a computer, a two-dimensional resistive mesh element distribution by placing a plurality of minimally sized square mesh elements in a grid pattern on a region of a circuit design; modifying, with the computer, the two-dimensional resistive mesh element distribution by recursively placing larger square mesh elements throughout the resistive mesh element distribution according to placement rules; simulating, with the computer, the resistance of the modified mesh element distribution; and outputting the simulation results to a display.
地址 San Jose CA US