Semiconductor integrated circuit device

摘要

A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation.

主权项

1. A semiconductor integrated circuit device comprising:
a plurality of memory cells; and a control circuit that controls the plurality of memory cells, wherein each of the memory cells has a transfer MOS transistor whose gate is connected to a word line, and the control circuit applies
a first voltage to the word line at the time of a write operation of the memory cell,a second voltage to the word line at the end of the write operation, anda third voltage to the word line in a preparation period after selecting the memory cell and before writing test data.