半导记忆体设备;SEMICONDUCTOR MEMORY APPARATUS

摘要

本发明揭示一种半导体记忆体设备，包括：一栏位址解码单元，其配置成解码一栏位址，并且产生一栏选择信号；一列位址解码单元，其配置成解码一列位址，并且产生一字线选择信号；一驱动驱动器单元，其配置成提供不同电压给复数个电阻式记忆体元件，以回应该栏选择信号；一吸收电流控制单元，其配置成产生具有不同电压位准的复数个吸收电压，以回应该字线选择信号；及复数个电流吸收单元，其配置成让电流从该等复数个各自电阻式记忆体元件供应至一接地端，以回应该等复数个吸收电压。; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.