Write level training using dual frequencies in a double data-rate memory device interface

摘要

A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined by the write-leveling procedure. The determination can then be used to ensure that the data strobe signals of all source synchronous groups are aligned with the same edge of the clock signal.

主权项

1. A write leveling calibration method in a dynamic random access memory (DRAM) interface, comprising:
setting a clock signal in the interface to a first frequency, the clock signal at the first frequency having a first period; performing a first write leveling method in the interface while the clock signal is set to the first frequency to obtain a first write leveling value; setting the clock signal in the interface to a second frequency, the clock signal at the second frequency having a second period, wherein one of the first period and the second period is an integer multiple of the other of the first period and the second period; performing a second write leveling method in the interface while the clock signal is set to the second frequency to obtain a second write leveling value; determining a first calculated value in response to the first write leveling value and the second write leveling value; determining a number of clock cycles of offset in response to the first calculated value; setting a write leveling value in the interface to one of the first write leveling value and the second write leveling value plus the number of clock cycles of offset; and setting the clock signal in the interface to one of the first frequency and the second frequency corresponding to the one of the first write leveling value and the second write leveling value.