EEPROM memory protected against breakdown of control gate transistors

摘要

The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply a first control voltage to a control terminal of the first control gate transistor through a first current limiter, and a second control circuit to supply a second control voltage to a control terminal of the second control gate transistor through second current limiter.

主权项

1. An electrically erasable and programmable memory comprising:
a word of memory cells each including a floating gate transistor; a first control gate transistor configured to apply a control gate voltage to the floating gate transistors of the memory cells of the word; a second control gate transistor in parallel with the first control gate transistor and of a same conductivity type as the first control gate transistor, and configured to also apply the control gate voltage to the floating gate transistors of the word; and a control circuit configured to supply a first control voltage to a control terminal of the first control gate transistor and a second control voltage to a control terminal of the second control gate transistor, the control circuit including:
a first current limiter electrically coupled to the control terminal of the first control gate transistor and configured to limit current drawn through the first control gate transistor, anda second current limiter electrically coupled to the control terminal of the second control gate transistor and configured to limit current drawn through the second control gate transistor.