NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To secure a withstand voltage of a bit line connection transistor while suppressing an increase of a layout area of the bit line connection transistor.SOLUTION: An outside layout region R1 and an inside layout region R2 are provided in a layout region of a bit line connection circuit 9, bit line connection transistors are arranged in a matrix form in the outside layout region R1 and the inside layout region R2 so that a channel length direction coincides with a column direction, and a distance L3' in the channel length direction between a high concentration impurity diffusion layer 26 of each bit line connection transistor arranged in the outside layout region R1 and a corresponding element isolation region 22 is set longer than a distance L3 in the channel length direction between a high concentration impurity diffusion layer 26 of each bit line connection transistor arranged in the inside layout region R2 and a corresponding element isolation region 22.