Robust glitch-free clock switch with an unate clock network

摘要

A system, method, and computer program product are provided for the switching of clock signals. A clock network switching system includes a first re-synchronization circuit coupled to a first input clock, and a second re-synchronization circuit coupled to a second input clock. There is also an input select decoder coupled to the first and second re-synchronization circuit that can dynamically select either the first or the second input clock to be active. When an input clock is selected to be active, the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock where both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock.

主权项

1. A clock switching system, comprising:
a first re-synchronization circuit configured to receive a first input clock; a first OR gate logic circuit configured to receive the first input clock and an output from the first re-synchronization circuit; a second re-synchronization circuit configured to receive a second input clock; a second OR gate logic circuit configured to receive the second input clock and an output from the second re-synchronization circuit; an input select decoder coupled to the first re-synchronization circuit and the second re-synchronization circuit, configured to dynamically select either the first or the second input clock to be active; a feedback controller configured to:
feedback an output of the first re-synchronization circuit back into an input of the second re-synchronization circuit, andfeedback an output of the second re-synchronization circuit back into an input of the first re-synchronization circuit, a third OR gate logic circuit configured to receive the output feedback from the second re-synchronization circuit and an output from the input select decoder; and a fourth OR gate logic circuit configured to receive the output feedback from the first re-synchronization circuit and the output from the input select decoder; wherein upon being dynamically selected the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock, wherein both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock, wherein the feedback of the output of the first re-synchronization circuit is synchronized with the feedback of the output of the second re-synchronization circuit, and wherein the first input clock into the first re-synchronization circuit, and the second input clock into the second re-synchronization circuit, are not inverted.