| 发明名称 |
VERTICAL NANOWIRE BASED HETERO-STRUCTURE SPLIT GATE MEMORY |
| 摘要 |
A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The first and second gates form a gate-all-around transistor of the memory cell. |
| 申请公布号 |
US2014159114(A1) |
申请公布日期 |
2014.06.12 |
| 申请号 |
US201213707617 |
申请日期 |
2012.12.07 |
| 申请人 |
GLOBALFOUNDRIES SINGAPORE PTE. LTD. |
发明人 |
ZHENG Ping;TOH Eng Huat;SUN Yuan |
| 分类号 |
H01L29/78;H01L29/66 |
主分类号 |
H01L29/78 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory cell comprising:
a vertical base disposed on a substrate, the vertical base includes first and second channels between top and bottom terminals; a first gate surrounding the first channel; and a second gate surrounding the second channel, wherein the first and second gates form a gate-all-around transistor of the memory cell.
|
| 地址 |
Singapore SG |
