| 发明名称 |
Time Interleaving Analog-to-Digital Converter |
| 摘要 |
A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs. |
| 申请公布号 |
US2014152477(A1) |
申请公布日期 |
2014.06.05 |
| 申请号 |
US201213706035 |
申请日期 |
2012.12.05 |
| 申请人 |
CREST SEMICONDUCTORS, INC. |
发明人 |
Lewis Donald E.;Kier Ryan James;Hales Rex K.;Haque Yusuf |
| 分类号 |
H03M1/50;H03M1/12 |
主分类号 |
H03M1/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A time interleaving Analog-to-Digital Converter (ADC), comprising:
a plurality of ADCs; a timing generator that generates a clock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate, and a circuit for adjusting the bandwidth of the plurality of ADCs.
|
| 地址 |
San Jose CA US |
